1. Technical Field
The present disclosure relates to digital-to-analog converters (DACs) and, more particularly, to high-speed low-resolution current steering DACs.
2. Description of Related Art
With the rise of the digital age, large amounts of information are transferred and stored in the form of digital signals over wired and wireless networks for a wide variety of applications. Such applications include, for example, digital television, streaming multimedia on a wireless device, online gaming, etc. Although signals are easily stored and transmitted in digital form, conversion of digital signals to analog signals is necessary for recognition by human senses or other non-digital systems.
With recent TV broadcasting technology evolutions, in some television broadcasting systems, TV signals are carried in different high frequency bands. TV modulators and demodulators need to support multiple carrier frequencies. In fact, pixel carriers may fall from several tens to several hundreds of MHz. Considering the situation when the first harmonic of the lowest frequency carrier may fall not far away enough from the highest carrier, a sharp reconstruct filter is desired. As a result, a more efficient DAC structure for this range of signal frequencies is current steering DAC. This is why current steering DACs tend to have higher speed and lower resolution in the digital-to-analog conversion. A current steering DAC may utilize one current source, for each bit of a digital code to be converted by the DAC, to provide a precise current or voltage to a summing point. These precise currents or voltages are summed up at the summing point to provide a converted analog signal. However, as high-precision current sources tend to be expensive, a hybrid approach, in which thermometric decoder and an array of 2n−1 identical unit cells are utilized for an n-bit digital code to be converted, is gaining popularity. This configuration tends to provide improved differential nonlinearity and minimized glitch energy.
For example, an 8-bit DAC may have an 8-bit thermometric decoder with each one of its 255 output bits controlling a unit current source. Accordingly, latching the thermometric code locally at the input of each unit cell is necessary for a number of reasons. First, there is basically no way to guarantee simultaneous settling of all 255 decoder's outputs across the unit cell array that would result in clock phase modulation with signal amplitude. Second, the usual two-step decoding of input code (row and column signals, locally AND-ORed) may result in clock feed-through even when a unit cell is not supposed to change state, and this may cause possible large glitches when row and column signals are misaligned. Third, it is imperative that the total logic delay between a clock source and the output of the unit cells be minimized in order to reduce variations across the cell array (due to mismatch) and across time (due to device noise) that would result in jitter. A conventional current steering DAC may include a thermometric decoder, 2n−1 latches and 2n−1 unit current cells, with each latch latching a respective thermometric code and driving the differential pair of p-type metal-oxide-semiconductor (PMOS) field effect transistors of the respective unit current cell to provide output analog signals outp and outn.
FIG. 5 depicts a gated D latch 505 which is typically used in conventional current steering DACs. FIG. 5 also illustrates a conventional latch 510, which is the schematic diagram of the latch 505. The latch 505 features inherent symmetry as needed for balanced enabling an disabling switching of the transistors in a respective unit current cell, provided that input signal D is settled before the enable signal E, e.g., a clock signal, is rising. The latch 505 outputs signals Q and QB feature in an inherent ‘break-before-make’ nature in that the falling of one output, e.g., pulled down by the left or right n-type metal-oxide-semiconductor (NMOS) field effect transistor stack, before the other output is rising so that both outputs Q and QB will cross each other at a low trip-point voltage. This ensures that, during the switching of the unit current cell, current is always flowing through the differential pair of PMOS transistors in the unit current cell. This in turn minimizes the occurrence of glitch, and prevents desaturation in cascades of PMOS transistors M2 and M1, and hence the long recovery that would result.
However, latch in the conventional current steering DAC still suffer from at least an issue of the output rising edge being inherently slow. Referring to the schematic diagram of the latch 510, PMOS transistors of the output inverters need to be weak enough, i.e., weaker than the NMOS transistors in the NMOS stack of the latch 510 that fight against the PMOS transistors during switching, and this is especially critical in the case of slow NMOS transistors/fast PMOS transistors. The aforementioned low trip-point voltage is achieved after some significant delay. On the one hand, the NMOS stack cannot pull one of the output voltage levels down to zero as long as the other output voltage level has not risen high enough so that an opposite PMOS transistor is turned off. This is slowing down the end of the falling edge of the pull-downed voltage level significantly. On the other hand, the rising edge is slow due to the PMOS transistors being purposely made weak. The trip point is reached as both output voltage levels change very slowly, and the actual value and timing of the trip point tend to vary not insignificantly between the unit current cells due to device mismatch.
Moreover, direct loading of latches, such as the latch 510, is undesirable. When the loading is above certain loading threshold, buffers may be used. Buffering the outputs of the latch may result in faster and smaller latch, lower power consumption, and minimized width of tail current peak. FIG. 5 also illustrates a latch 520 with a single-stage, and hence inverting, buffer. FIG. 5 further illustrates a latch 530 with a double-stage, and hence non-inverting, buffer.
With the latch 520, the inherent ‘break-before-make’ nature in the direct outputs of the latch 520 will result in the outputs Q and QB of the single-stage buffer having a ‘make-before-break’ nature: as a result, current would transiently stop from flowing in the unit cell at each switching, creating large glitches. To get the wanted ‘break-before-make’ nature after the inverting buffers, the latch itself should have a ‘make-before-break’ nature: this could be achieved with simply using the CMOS-complementary version of latch 520, depicted on Figure X. However, it is highly undesirable to use such version X, as it would entail forcing the NMOS transistor in each of the cross-coupled inverters with two PMOS in series. PMOS being about 4 times weaker than NMOS, this would result in about 4 time higher load on clock signal EB to get the same switching speed.
With the latch 530, the load threshold in order for such implementation to be a solution preferred over the latch 510 would be much higher. Thus, it is not practical to use the buffered latch 530.